Introducing the IBM zEnterprise BC12 and EC12 Updated Hardware: Processor, Memory, System Structure, and Installation Planning

Project and Program: MVS, MVS Core Technologies

Tags: Proceedings, SHARE in Anaheim 2014, 2014

Come to this session for a "deep dive" technical introduction to the processor design, architectural enhancements, and overall system structure of the new IBM zEnterprise BC12  (zBC12) and EC12 (zEC12) updates for GA2, announced on July 23, 2013. Material presented will include considerable technical detail on zBC12 enhancements compared to z114 and z10 BC in the areas of the processor chip, additions to z/Architecture, single-chip modules, cache hierarchy, processor drawer structure, memory offerings, cryptographic function, OnDemand offerings, and installation flexibility. Corresponding updates to the zEC12 at GA2 will also be included. A brief introduction to the new zBC12 I/O infrastructure will also be included for completeness. For a complete introduction to zBC12 I/O infrastructure and GA2 updates to zEC12 I/O infrastructure, plan to attend session 13706: Introducing the new IBM zEnterprise BC12 and EC12 Updated Hardware: I/O Subsystem, I/O Features, and Parallel Sysplex Coupling Function.-Harv Emery-IBM Corporation

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