IBM zEnterprise 196 (z196) and zEnterprise 114 (z114) Hardware Overview and Update

Project and Program: MVS, MVS Core Technologies

Tags: Proceedings , 2012 , SHARE in Atlanta 2012

Come to this session for a detailed technical overview of both the IBM zEnterprise 196 (z196) and 114 (z114) and an update on new features and functions announced in recent announcements  following SHARE in Orlando. The material presented will include considerable technical detail on zEnterprise server design and function: processor design including z196 processor book structure, z114 processor drawer structure, enhanced cache design and out of order instruction execution; memory design including redundant array of independent memory (RAIM) technology and z196 and z114 memory offerings; and I/O subsystem structure, including a brief introduction to I/O infrastructure.  A "deep dive" on the new zEnterprise PCI Express and InfiniBand I/O infrastructures common to the z196 and z114 will be presented in session 10617, "Introducing the new z196 and z114 PCIe I/O and Coupling Infrastructure". A road map will be offered to other zEnterprise System technical topics to be presented in other sessions, including "deep dive" sessions on the zEnterprise hardware including the zEnterprise BladeCenter Extension (zBX) - Session 10607, and System z Capacity on Demand - Session 10869. This session is an updated and consolidated version of two sessions given at SHARE in Orlando. It assumes a general background in previous System z servers, z/Architecture, and System z operating systems. Harv Emery, IBM Corporation

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