Optimizing Processor Cache on z13 and z14 Processors

Project and Program: MVS, MVS Core Technologies

Tags: Proceedings , 2018 , SHARE St. Louis 2018

Delivered capacity on z13 and z14 processors is more dependent than ever before on effective utilization of processor cache.  Since it is likely that one-third to more than half of your total CPU cycles are spent waiting for data to be staged into level 1 processor cache, it is critical to understand and have visibility into this significant component of your CPU consumption.  Attendees of this session will learn how to interpret the SMF 113 metrics to optimize your environment and potentially reduce CPU and thus MLC software expense.
 
z14 processor cache design changes will be a primary focus of the session.  Multiple z14 case studies will be reviewed to observe the impact of those changes on delivered capacity.  Based on this analysis, attendees will gain an understanding of what they can expect from a z14 migration in their environments, whether to anticipate their capacity increase to be at the upper or lower end of the published ranges.
 
Overall, the presentation incorporates findings and case studies gleaned from reviewing detailed processor cache data from more than 50 sites across 5 countries.  This core content has recently been recognized with SHARE Best Session and CMG Best Paper awards.-Todd Havekost-IntelliMagic

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