Optimizing Processor Cache on z13/z14/z15 Processors

Project and Program: MVS, MVS Performance

Tags: Proceedings , 2020 , SHARE Fort Worth 2020

Now that significant cycle speed improvements are a thing of the past, delivered capacity on processors beginning with the z13 is more dependent than ever before on effective utilization of processor cache.  Since it is likely that one-third to more than half of your total CPU cycles are spent waiting for data to be staged into level 1 processor cache, it is critical to understand and have visibility into this significant component of your CPU consumption.
z14 & z15 processor cache design changes will be a primary focus of the session.  Multiple case studies will be reviewed to observe the impact of those changes on delivered capacity.  Based on this analysis, attendees will gain an understanding of what they can expect from z14 and z15 migrations in their environments, whether to anticipate their capacity increase to be at the upper or lower end of the published ranges.
This is not ivory tower theory … every main point in this presentation is backed up with real-life case studies.  And though these concepts have been presented at previous SHARE conferences, the presentation continues to be enhanced with additional before-and-after data from sites quantifying the CPU reductions they have achieved through more effective utilization of processor cache.  Overall, findings gleaned from reviewing detailed processor cache data from more than 70 sites across 8 countries are summarized in this information-packed hour.  This core content has been recognized with SHARE Best Session and CMG Best Paper awards.-Todd Havekost-IntelliMagic

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