SHARE Live!: Achieving Significant Capacity Improvements on the IBM z13: User Experience
Project and Program:
MVS,
MVS Performance
Tags:
Proceedings,
2016,
SHARE in San Antonio 2016
One of the dominant themes of the z13 processor announcements is that delivered capacity is becoming increasingly dependent on effective utilization of processor cache. Benefit from the experiences of a user; who initially experienced a capacity shortfall migrating from zEC12 to z13 models; but ultimately achieved significant capacity improvements through a series of configuration changes. This session will review metrics associated with changes including increasing the number of hardware CPs; LPAR topology; and maximizing the number of Vertical High CPs in the Hiperdispatch configuration. Various benefits of deploying "excess" hardware capacity will also be covered.-Todd J. Havekost-USAA
Back to Proceedings File Library